1. Field of the Invention
This invention relates to an integrated circuit arithmetic logic unit and more particularly to an arithmetic logic unit bit-slice implemented on a single semiconductor substrate having logic control also implemented on that substrate for causing the performance of algorithms such as multiply and divide designed so that a plurality of bit-slices may be concatenated to provide any desired word size with appropriate built-in control for causing the performance of the above mentioned algorithms for the entire word.
2. Description of the Prior Art
In the digital computer art, it was common practice to provide a computer having a fixed word length arithmetic logic unit. That is, the work length might be 32 bits or 64 bits with the computer having the control hardware to cause the arithmetic logic unit to operate. The operations typically included a simple add and subtract and also included iterative sequence algorithms such as multiply and divide. The adders of the arithmetic logic units were provided with circuitry for carry or borrow.
As integrated circuitry became commonplace, arithmetic logic units having short word lengths, such as four bits became available. These units are known as bit-slices. These bit slices contained borrow or carry logic and could be concatenated, but logic for algorithms such as multiply, divide and cyclic redundancy character generation had to be provided by outside control.
Using Large Scale Integration (LSI) techniques, the arithmetic logic unit bit-slice disclosed herein was implemented. It is of a short word length (four bits in the preferred embodiment) and provided with carry logic, but more importantly is provided with circuitry for identification of the arithmetic logic unit bit-slice within a larger word and with control logic, reactive to the bit-slice position, that enables the performance of algorithms such as multiply, divide, and cyclic redundancy character generation.